The present invention relates to a wiring board having a stiffener.
One of the conventional wiring boards is a wiring board having a stiffener for reducing a warp of a wiring board main body (see FIG. 1).
FIG. 1 is a cross-sectional view of the conventional wiring board.
Referring to FIG. 1, the conventional wiring board 200 has a wiring board main body 201 and a stiffener 202.
The wiring board main body 201 is a coreless substrate, having a semiconductor device attaching pad 211, the dielectric layers 212 and 216 made of resin material, the via holes 213 and 217, a wiring pattern 215, an external connection pad 218, and a solder resist layer 221.
The semiconductor device attaching pad 211 has an attaching surface 211A on which a semiconductor device 204 is attached. The semiconductor device attaching pad 211 is disposed inside a dielectric layer 212 so that the attaching surface 211A and a surface 212A of the dielectric layer 212 may be almost flush. A solder 208 for fixing an internal connection terminal 206 provided on an electrode pad 205 of the semiconductor device 204 onto the semiconductor device attaching pad 211 is provided on the attaching surface 211A.
The dielectric layer 212 is an insulation layer for forming the semiconductor device attaching pad 211, a via hole 213, and the wiring pattern 215. The dielectric layer 212 has an opening portion 223 for exposing a surface 211B of the semiconductor device attaching pad 211 (surface of the semiconductor device attaching pad 211 located on the opposite side of the attaching surface 211A).
The via hole 213 is provided in the opening portion 223. One end portion of the via hole 213 is electrically connected with the semiconductor device attaching pad 211, and the other end portion of the via hole 213 is integrated with the wiring pattern 215.
The wiring pattern 215 has a pad 225 and a wiring 226. The pad 225 is provided on a surface 212B of the dielectric layer 212. The pad 225 is integrated with the wiring 226. The pad 225 is electrically connected via the wiring 226 with the via hole 213. The wiring 226 is provided on the surface 212B of the dielectric layer 212. The wiring 226 is integrated with the via hole 213 and the pad 225. The wiring 226 electrically connects the via hole 213 and the pad 225.
The dielectric layer 216 is provided on the surface 212B of the dielectric layer 212 to cover the wiring 226. The dielectric layer 216 has an opening portion 228 for exposing a surface 225A of the pad 225.
The via hole 217 is provided in the opening portion 228. One end portion of the via hole 217 is electrically connected with the pad 225, and the other end portion of the via hole 217 is integrated with the external connection pad 218.
The external connection pad 218 is provided at the other end portion of the via hole 217 and on a surface 216A of the dielectric layer 216. The external connection pad 218 is electrically connected via the via hole 217 with the pad 225. The external connection pad 218 has a terminal disposition surface 218A on which an external connection terminal 210 is disposed. The external connection pad 218 is electrically connected via the external connection terminal 210 with a packaging board 209 such as a mother board.
The solder resist layer 221 is provided on the surface 216A of the dielectric layer 216. The solder resist layer 221 has an opening portion 221A for exposing the terminal disposition surface 218A.
FIG. 2 is a plan view of a stiffener as shown in FIG. 1.
Referring to FIGS. 1 and 2, the stiffener 202 has a frame shape in plan view, and is bonded by an adhesive 203 to the surface 212A of the dielectric layer 212. The stiffener 202 has the opening portion 202A for exposing a semiconductor device attaching area M. The opening portion 202A is the opening portion for receiving the semiconductor device 204 attached on the wiring board main body 201. As the parent material of the stiffener 202, for example, a metal plate or a glass epoxy substrate may be employed. Also, as the adhesive 203, for example, a liquid or sheet like epoxy resin having the same composition as the resin used for the dielectric layers 212 and 216 may be employed.
In this manner, the warp of the wiring board main body 201 can be reduced by providing the stiffener 202 on the wiring board main body 201 where the warp is likely to occur.
FIGS. 3 to 8 are views showing the manufacturing process for the conventional wiring board, and FIG. 9 is a plan view of the conventional stiffener parent material. In FIGS. 3 to 9, the same or like parts are designated by the same reference numerals or signs as the conventional wiring board 200.
Referring to FIGS. 3 to 9, a manufacturing method for the conventional wiring board 200 will be described below. At first, in the process as shown in FIG. 3, a board 232 in which the plurality of wiring board main bodies 201 are integrally made on an upper surface 231A of a carrier 231 having a plurality of wiring board main body formation areas H having conductivity and formed with the wiring board main bodies 201 is formed by a well known method.
Next, in the process as shown in FIG. 4, the carrier 231 as shown in FIG. 3 is removed. Next, in the process as shown in FIG. 5, the board 232 as shown in FIG. 4 is turned upside down, and the solder 208 is formed on the attaching surface 211A of the semiconductor device attaching pad 211 provided on the board 232.
Next, in the process as shown in FIG. 6, a stiffener parent material 233 (see FIG. 9) having a plurality of opening portions 202A is formed by working a metal plate or glass epoxy substrate, and then the board 232 and the stiffener parent material 233 are disposed oppositely so that the semiconductor device attaching area M and the opening 202A may be confronted. The stiffener parent material 233 is a member cut at a cutting position 1 to become a plurality of stiffeners 202 (see FIGS. 1 and 2).
Then, in the process as shown in FIG. 7, the stiffener parent material 233 is bonded on the surface 212A of the dielectric layer 212 by the adhesive 203. Thereby, a structure corresponding to a plurality of wiring boards 200 is formed.
Then, in the process as shown in FIG. 8, the plurality of wiring boards 200 are individuated by cutting the board 232 and the stiffener parent material 233 in a part corresponding to the cutting position 1. In cutting the board 232 and the stiffener parent material 233, for example, a dicer or slicer may be employed (e.g., refer to patent document 1).    [Patent document 1] JP-A-2000-323613
However, in the manufacturing method for the conventional semiconductor device 200, the excess adhesive 203 swells out onto the surface 212A of the dielectric layer 212 in a part corresponding to the semiconductor device attaching area M when the stiffener parent material 233 is bonded onto the surface 212A of the dielectric layer 212 (hereinafter some adhesive 203 swelling out onto the surface 212A of the dielectric layer 212 in a part corresponding to the semiconductor device attaching area M is called a “swell-out part N”).
Therefore, in the case where the height of the swell-out part N of the adhesive 203 is greater than the height of the internal connection terminal 206, the semiconductor device 204 and the swell-out part N of the adhesive 203 are contacted, whereby there is a problem that an electrical connection failure occurs between the internal connection terminal 206 and the semiconductor device attaching pad 211. In other words, there is a problem that the electrical connection reliability between the semiconductor device attaching pad 211 provided on the wiring board main body 201 and the semiconductor device 204 is decreased.